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Luisa Gutierrez replied to the topic Discussion Topic: Verification vs. Validation in the forum The Design History File 8 years, 2 months ago
The verification is when the tests are created for each specification in the DSD to confirm that the design input equals the design output. For instance, if the device is design to be coated black and it was incorrectly coated, it is already failing one of the verification tests. Design validation is when the design output or the device completed meets the user needs, intended uses and applicable standards. This is crucial to check that the product placed in the market is meeting the customer’s standards or can cause product recalls.
In terms of the Design and Process V&V, they are both similar due to still working to create the same product and must at the end of both still work to meet the user needs. So in terms of the validation of the product at the end of production, the outcome must be the same. However, in terms of the verification process, there would be some differences due to the scale of the process. For instance, within the manufacturing after the design transfer, other items that must be taken into consideration such as equipment to create device, materials and availability. It is important to make sure each output from each equipment meets the input based on the specification requirements.
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