Validation and verification are frequently mentioned in tandem. They’re often called V&V.

To get a good understanding of this, I wanted to add a few points that would explain the difference a little better.The literal meaning of validation means “the process of checking that something satisfies a certain criterion,”and verification can mean: “additional proof that something that was believed is correct”

A key distinction between design verification and design validation activities is that verification only requires that a single unit be assessed. What constitutes that single unit will vary depending on the intent of the verification. It might be one batch of raw material (for material performance tests), one machined part (for first article inspection), on one package sample (for integrity tests). The intent of verification is to confirm that the design outputs (i.e., the materials or components specified in design documents) meet the design input requirements.

Validations, on the other hand, require that studies be conducted to ensure that the device can be manufactured to meet design specifications on a consistent basis (i.e., process validation), and to ensure that the finished device is safe and effective for its intended purpose (i.e., design validation). For the process validation, multiple devices must be manufactured and evaluated to confirm that the production process is capable of producing devices within specifications on a consistent basis. For the design validation, multiple devices must be used to treat multiple patients to confirm that the treatment is safe and effectively.