Regarding verification and validation themselves, the difference lies in what is being confirmed. Verification is the confirmation that the design output meets the design input requirements. Verification is showing that what the project defined as their requirements of the design came out successful. Validation is the assurance that the device meets the user needs and how it is intended to be used. The importance of validation is simulated use.

Within the V&V process for Design versus Process, there is an overlap but there also exists divides. Both are ensuring a safe and effective device, but at different points of the manufacturing. For Design V&V, it is ensuring that the outputs of the design are consistent with what was specified as an input, as well as ensuring simulated use. For Process V&V, it is confirming that the process is consistent and produces the same results every time it is carried out so that the device will be produced consistently, with the overarching goal for a safe and effective device.