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  • asimbana replied to the topic Discussion Topic: Verification vs. Validation in the forum The Design History File 7 years, 2 months ago

    Verification = Inputs = Outputs
    Verification is completed after DAD and RA, this document shows the tests that were created for each specification or requirement in the DSD to verify that the design input meets the needs of the design outputs. This document will have a protocol on how the the test plan for each requirement is setup and the report for the actual statistical analysis, outcome and pass or fail status of the test. Validation is when the output of the design meets the user needs and it’s intended uses. This document will also make references to the DSD but also to the DID and IFU along with regulations and also materials. This is important to ensure that the outcome of the product does not stray away from the needs of the customer.

    In terms of the V&V having overlapping sections, yes that would be when referencing testing for safety and efficacy but also the performance of the device, however they differ in terms of the approach and processes.